The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A FET includes a gate electrode structure as a control electrode and spaced apart source and drain electrodes between which a current can flow. A control voltage applied to the gate electrode structure controls the flow of current through a channel region between the source and drain electrodes.
The gain of an MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility (μ) of the majority carrier in the transistor channel. The current carrying capability and hence the performance of a MOS transistor is proportional to the transconductance times the width of the channel region divided by the length of the channel region (gmW/l). The mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor, and the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor, are at least partially dependent upon the width and length of their corresponding channel regions that are defined by the position of the corresponding source and drain regions including the source and drain extensions and Halo implants. Typically, the source and drain extensions and Halo implants are positioned adjacent to and offset from their corresponding gate electrode structures using sidewall spacers or offset spacers as ion implantation masks. However, current manufacturing methods typically form the sidewall spacers for the PMOS transistors and the NMOS transistors such that the widths of the sidewall spacers, which define the offset of the source and drain extensions and Halo implants from their respective gate electrode structures, are essentially the same. Performance and design requirements vary for a variety of different IC applications. It would be desirable for some of these applications to have the flexibility to use sidewall spacers with different widths to form, for example, source and drain extensions and Halo implants defining dimensionally different channel regions for some or all of the MOS transistors, such as, for some or all of the PMOS transistors and/or for some or all of the NMOS transistors.
Accordingly, it is desirable to provide methods for fabricating semiconductor devices by forming sidewall spacers with different widths. Moreover, it is desirable to provide methods for fabricating semiconductor devices using sidewall spacers with different widths to form the source and drain extensions and Halo implants for some or all of the MOS transistors to define dimensionally different channel regions. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.